1. Field of the Invention
The present invention relates to a system in package and particularly to a system in package that integrates a chip including a Central Processing Unit (CPU) used in common for a plurality of products and a custom chip including a different wiring layer for each user to implement different specifications into one package.
2. Description of Related Art
Recent semiconductor apparatus integrate the maximum number of functional blocks constituting a system in order to implement many functions with a small mounting area. One of such semiconductor apparatus is a System on Chip (SoC) in which a plurality of functional blocks are formed on a single semiconductor chip. A SoC implements all functional blocks in one semiconductor process. However, some kind of functional blocks cannot be implemented by the process or have low efficiency in manufacturing the process. For example, if a chip size is too large due to the need for mounting a high-capacity memory or the like, the percentage of non-defective items decreases significantly to fail to manufacture a semiconductor chip. Further, to implement both of a function to be used in common by a plurality of users (which is referred to hereinafter as a common function) and a function with different specifications for each user (which is referred to hereinafter as an individual function) it is necessary for a SoC to design and manufacture a semiconductor chip for each user in any case. Thus, the use of a SoC tales a long development period and requires a high development cost.
In order to overcome such drawbacks, a System in Package (SiP) approach is applied for semiconductor apparatus. The SiP integrates a plurality of semiconductor chips, which form a system, into one package. With the use of a SiP, for example, it is possible to implement a common function on one semiconductor chip (which is referred to hereinafter as a common chip) using a most-advanced fine process while implementing an individual function for each user on a semiconductor chip (hereinafter as an individual chip) that is different from the common chip using a previous generation process. It is also possible to design and manufacture a common chip in advance and then design and manufacture an individual chip only later according to the specifications of a user, which enables reduction of a development period and a development cost. Further, because a SiP allows connection of different chips, a limitation on chip size is significantly less than a SoC. A module that integrates a plurality of semiconductor chips, regardless of their functions, is sometimes called a Multi Chip Module (MCM).
Examples of a SiP are disclosed in Japanese Unexamined Patent Application Publication Nos. 10-111864 (related art 1) and 2000-223657 (related art 2). The semiconductor apparatus described in the related arts 1 and 2 are a SiP or a MCM with the lamination of a main chip of the largest size and a sub chip of the smaller size placed on top of the main chip. In the semiconductor apparatus, the sub chip has a connection terminal of a Ball Grid Array (BGA) type on its bottom surface. The main chip includes a pad on its top surface at the position corresponding to the connection terminal of the sub chip. The sub chip is mounted on the main chip to thereby integrate them into one package. The semiconductor apparatus that packages semiconductor chips in a laminated structure is called a Chip on Chip (CoC).
Another example of a SiP is disclosed in Japanese Domestic Re-publication of PCT Publication No. WO2002/57921 (related art 3). The semiconductor apparatus of the related art 3 is a MCM for detecting a defect at an early stage during the development of a SoC. In the MCM, a plurality of semiconductor chips for implementing the functions to be packaged in a SoC are mounted on a build-up substrate. Particularly, a Field Programmable Gate Array (FPGA) that allows a logic circuit to be programmable is mounted on the build-up substrate. It is thereby possible to implement an individual function for each user and check a defect at an early stage. Further, in order to achieve the high speed communication and highly accurate reproduction in a SoC, it is necessary to integrate the semiconductor chips on the build-up substrate (which is referred to hereinafter as a module substrate) with high density. For the high-density integration, the related art 3 integrates a semiconductor chip in Chip Size Package (CSP) having terminals of the BGA type with face-down positioning, thereby reducing a space between adjacent semiconductor chips.
However, according to the related arts 1 and 2, in the event of a change in the position of the sub chip terminal or in the size of the sub chip, it is necessary to redesign the main chip so as to change the position of pads of the main chip. According to the related art 3, in the event of a change in a semiconductor chip to be mounted on the module substrate, it is necessary to redesign the module substrate according to the modified structure of the semiconductor chip in order to accurately reproduce the characteristics of a SoC. The redesign leads to a longer development period and a higher development cost.